zilog w orldwide h eadquarters ? 910 e. h amilton a venue ? c ampbell , ca 95008 t elephone : 408.558.8500 ? e mail : csupport @ zilog . com ? i nternet : http :// www . zilog . com p roduct b lock d iagram f eatures ? two independent, 0 to 10 mbps, full-duplex chan- nels, each with two baud-rate generators (brgs) and one digital phase-locked loop (dpll) for clock recovery ? 32-byte data fifos for each receiver and trans- mitter ? async mode with: C 1C8 bits/character; 1/16 to two stop bits/charac- ter in 1/16 bit increments C programmable clock factor C break detect and generation C odd, even, mark, space, or no parity and fram- ing error detection ? byte-oriented synchronous mode with C 1C8 bits/character C 2- to 16-bit programmable sync character C 16- or 32-bit cyclic redundancy check (crc) and transmit-to-receive slaving (for x.21) ? hdlc/sdlc mode with: C 8-bit address compare C extended address ?eld option C 16- or 32-bit crc C programmable idle line condition C optional preamble transmission and loop mode ? external character synchronous mode for receive ? dma interface with separate request and acknowledge for each receiver and transmitter g eneral d escription the z16c30 usc? universal serial controller is a dual-channel multi-protocol data communications peripheral. designed for use with any conventional multiplexed or non-multiplexed bus, the usc functions as a serial-to-parallel, parallel-to-serial converter/controller, and may be software con?gured to satisfy a wide variety of serial communications applications. the device contains a variety of sophisticated internal functions, including two baud rate generators per channel, one digital phase-locked loop per channel, character counters for both receive and transmit in each channel, and 32-byte data fifos for each receiver and transmitter. the cpu bus accesses have been shortened from 160 ns per access to 110 ns per access. the usc has a transmit and receive clock range of up to 10 mhz (20 mhz when using the dpll, brg, or ctr to divide the clock by 2 or more), and data transfer rates as high as 10 mbps (full duplex). the usc handles asynchronous formats, synchronous byte-oriented formats such as bisync, and synchronous bit-oriented formats such as hdlc. the device generates and checks crc in any synchronous mode and can be programmed to check data integrity in various modes. the usc also has facilities for modem controls in both channels. in applications where these controls are not needed, the modem controls may be used for general-purpose i/ o. the same holds true for most of the other pins in each channel. interrupts are supported with a daisy-chain hierarchy, with the two channels having completely separate interrupt structures. modem/control logic ctr brg dpll brg ctr crc transmit logic receive logic crc fifo fifo fifo transmit logic receive logic fifo crc crc ctr brg dpll brg ctr modem/control logic z16c30 usc? u niversal s erial c ontroller pb000300-scc0399
zilog w orldwide h eadquarters ? 910 e. h amilton a venue ? c ampbell , ca 95008 t elephone : 408.558.8500 ? e mail : csupport @ zilog . com ? i nternet : http :// www . zilog . com high-speed data transfers through dma are supported by a request/acknowledge signal pair for each receiver and transmitter. the device supports automatic status transfer through dma and device initialization under dma control. a pplications and s upport t ools the following development tools are available for the programming and debug of this device: ? z16c3001zco isa bus evaluation board ? z8018600zco evaluation board r elated p roducts similar communication controllers available from zilogs scc family include: to order, contact your nearest zilog sales of?ce or send an email to: csupport@zilog.com receive dma control to other channel receive fifo 32 bytes receiver interrupt control cpu i/o and device status clock mux 1. dpll 2. counters 3. brg0 4. brg1 receive/ transmit clocks transmit data receive data (32-byte) transmit fifo channel control transmit dma control i/o data buffer transmitter 16-bit internal data bus z8030 z8530 nmos scc (serial communication controller) z80c30 z85c30 cmos scc (serial communication controller) z16c35 iscc single channel scc with built-in dma controllers z80230 z85230 escc (enhanced serial communication controller) z16c32 iusc single channel usc with built-in dma controllers o rdering i nformation psi description z16c3010asc 100-pin vqfp usc device z16c3010vsc 68-pin plcc usc device z16c3001zco isa bus evaluation board z8018600zco 80186 evaluation board
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